1. Field of the Invention
This invention generally relates to data processing systems and more specifically to the interchange of data between a main memory unit and the central processor unit or input/output controllers in such data processing systems.
2. Discussion of the Prior Art
A data processing system usually includes a central processing unit (CPU) which executes software instructions which are stored at addresses, or locations, in main memory. These software instructions are transferred to the CPU sequentially under the control of a program counter. The data that is processed is transferred into and out of the system by way of input/output devices, or peripheral devices, such as teletypewriters, magnetic disks, magnetic tapes or line printers. Usually the data is temporarily stored in the main memory before or after the processing by the central processing unit.
In a system having a plurality of devices coupled over a common bus, an orderly system must be provided by which bidirectional transfer of information may be provided between the main memory and such other devices. In particular, apparatus must be provided to detect an attempt by a device connected to the common bus to access a main memory location not present in the system. This problem becomes more complicated when main memory is contained in more than one main memory unit. The problem is further complicated if the system has more than one common bus to which any of the main memory accessing devices can be connected.
Various methods and apparatus are known in the prior art for detecting attempts to access a nonexistent main memory location. One such structural scheme is shown in U.S. Pat. No. 4,001,790 issued to George J. Barlow, entitled "Modular Addressable Units Coupled in A Data Processing System Over A Common Bus" (hereinafter referred to as Barlow).
Barlow discloses a system in which one or more main memory units are connected to a common asynchronous communications bus along with the CPU and one or more input/output controllers to which peripheral devices are connected. In this particular scheme, each main memory unit contains a configuration switch that is set when the system is installed to the address of the lowest location contained in the particular main memory unit. Further, logic is provided to indicate the amount of memory in the particular main memory unit thus allowing each main memory unit to determine the highest address of a location in the particular main memory unit. When another device, CPU or peripheral device I/O controller, on the common bus wants to access a main memory location, the accessing device places the address of the main memory location on the common bus along with an indicator that the request is a memory read or memory write request. Each main memory unit examines the address and if the address falls within the range of locations contained in the main memory unit that particular main memory unit gives a positive acknowledgment on the common bus to the memory requesting device and then proceeds to access the addressed main memory location and perform the indicated memory read or write operation.
During all attempted main memory accesses, the CPU monitors the common bus to see if one of the main memory units gives a position acknowledgment to the memory requesting device and if no unit gives a positive acknowledgment within a preset time period, the CPU generates a negative acknowledgment which is placed on the common bus. In this scheme the CPU monitors the common bus even for those memory requests coming from I/O controllers so that the CPU can generate the negative acknowledgment if no main memory unit gives a positive acknowledgment.
Barlow further provides that main memory parity errors are signaled to the memory requesting device by common bus signals that are separate from those used to signal a positive or negative acknowledgment to a memory request. Each device on the common bus that accesses main memory has logic for receiving the positive acknowledgment, negative acknowledgment and parity error signals from the common bus so that appropriate status errors can be stored for examination by the software program.
The Barlow and similar schemes have the disadvantage that each main memory unit must have logic to generate a positive acknowledgment if the addressed location is within the particular main memory unit. Further, system response time is slowed up, and therefore data rates reduced, because the CPU monitor must be set to wait for the worst case response time of any main memory unit's positive acknowledgement before it can generate the negative acknowledgment. Further, logic must be provided in each device on the common bus that accesses main memory to receive a positive acknowledgment, a negative acknowledgment and memory parity error signals. A further disadvantage of this scheme is that: if these three signals are placed on the common bus in parallel, the bus must be wider (i.e., contain more lines); or if placed on the common bus in series, timing logic must be provided in each device and system device rates will be reduced.